(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of preventing auto-doping from the top polysilicon layer of a capacitor in the manufacture of integrated circuits.
(2) Description of the Prior Art
In the manufacture of integrated circuit devices, a so-called mixed-mode product fabrication is one in which MOSFET device structures and capacitor structures are formed on the same wafer. A capacitor is formed by using two polysilicon layers as the top and bottom plates of the capacitor with a dielectric layer therebetween. The polysilicon layers are formed either by in-situ polysilicon deposition or POCl-doped polysilicon. In either case, the dopant; that is, phosphorus; is spread throughout the polysilicon layer and tends to diffuse out of the polysilicon in post-poly etch thermal cycles. The out-diffused dopants will reach the silicon surface if the oxide on the surface is not thick enough to prevent further diffusion into the substrate in subsequent thermal processes. In a PMOS device on the same wafer, the out-diffused phosphorus will laterally and vertically increase the n-type dopant concentration near or under the edge of the channel region after thermal cycles. This is called auto-doping.
FIG. 1 illustrates this auto-doping phenomenon. A capacitor 50 has been fabricated overlying a field oxide region 12 on a semiconductor substrate 10. The capacitor comprises a polysilicon bottom electrode 41, dielectric layer 43, and top polysilicon electrode 45. Elsewhere on the wafer, a PMOS gate electrode device 52 has been formed. During thermal cycles, dopant 55 from the top capacitor electrode 45 out-diffuses into the atmosphere and into the substrate at the edge of the PMOS channel region 57. Because of the n-type dopant near the channel region, higher gate voltage will have to be applied to invert the channel region in order to form a conducting channel from source to drain. This results in a threshold voltage (V.sub.t) shift. In auto-doping, the n-type dopants come from the same wafer on which the PMOS devices are fabricated, as illustrated in FIG. 1, or dopants may come from the wafers positioned either before or after the wafer on which the PMOS devices are fabricated.
It is desired to prevent auto-doping. Two approaches to preventing auto-doping can be adopted. In one approach, the thickness of the oxide on the surface of the substrate can be increased so that it can retard the penetration of dopants. This approach is taught in the prior art of U.S. Pat. No. 5,461,002 to Safir and in U.S. Pat. Nos. 5,492,868 to Lin et al and 4,925,809 to Yoshiharu et al.
A second approach to preventing auto-doping is to prevent the out-diffusion of dopants from the n-type capacitor plate. This approach is taught in U.S. Pat. Nos. 5,070,382 to Cambou and 4,894,349 to Saito et al.
A third approach does not prevent auto-doping, but etches away those areas that have been auto-doped. This approach is taught in U.S. Pat. No. 5,461,002 to Safir.
The process of the present invention takes the second approach of preventing out-diffusion of dopants from the capacitor plate.